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用vhdl代码写的并行转串行的程序,波形图正确,已经在板子上运行过,良好-using VHDL code written in parallel to serial procedures waveform correct, the board has been running that good
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这是一个用VHDL语言编写的并口转串口程序，在altera开发系统下验证通过，运用于开发板与计算机之间的通信，源程序可以提供参考-This is a use of the VHDL language Parallel to Serial procedures, In altera development system under test passed, the development of applied between the panels and computer communicatio
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该模块主要完成并串转换功能。其中system_clk是输入并行时钟的频率，它是串行时钟serial_clk的八倍。byte_data_en是输入并行数据使能信号，byte_data是输入并行数据。serial_data是转换后的串行数据，bit_data_enable是串行数据有效信号。,The module main is completed and the string conversion functions. System_clk which is an input parallel c
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并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码，经Quartus II 5.1验证可用,String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
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串行输入并行输出 用vhdl语言描述的 有源代码主打色,Serial input parallel output using vhdl language to describe the main color of the source code
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pie编码器,将串行数据并行输出的一种常用编码-pie encoder, parallel to serial data output of a common coding
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This file recieves the serial data from the UART and forward to Serial To Parallel module
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本文件是可以直接使用下载到FPGA里面使用，里面包含时钟分频电路，串并转换和并串转换电路，多通道信号加权的乘加电路等。-The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation
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This project is "digital serial multiplier". this proh=ject is used to multiply the serial data with parallel data. the source code is writtenby using vhdl.
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parallel to serial data converter using VHDL
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实现窗口搜索算法的并行系统——序列存储器-Search algorithm to achieve the window parallel systems- Serial Memory
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this code is designed to perform parallel to serial operation it is very essential in every design
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这是一个将6组并行数据串行输出的VHDL源码，配合外部电路可以输出正负脉冲，还附有逻辑图哦。-This is a group of parallel data to serial output 6 of the VHDL source code, with the external circuit can output positive and negative pulses, also with a logic diagram oh.
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vhdl code to change the bits stream from parallel to serial
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包含16位CRC的并行实现和串行实现，并有测试程序。-Includes 16-bit CRC of the parallel and serial implementation to achieve, and test procedures.
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用软件实现CRC校验码计算很难满足高速数据通信的要求， 基于硬件的实现方法中， 有串行经典算法LFSR,电路以及由软件算法推导出来的其它各种并行计算方法。以经典的LFSR,电路为基础， 研究了按字节并行计算CRC校验码的原理.-Implemented in software CRC checksum calculation is difficult to meet the requirements of high-speed data communications, hardware-based
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ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明：
Filename Function
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dds_controller.vhd top entity, opcode decoding
ddslib.vhd configuration,opcode definition
dds_serial.vhd parallel to s
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此设计主要是完成音频I2S格式数据流的串并转换和并串转换,用VHDL描述-This design is to complete the audio I2S format data stream serial to parallel conversion and parallel to serial conversion in VHDL
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parallel to serial code vhdl
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This page of VHDL source code covers 2 bit parallel to serial vhdl code and provides link to 2 bit serial to parallel conversion.
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